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ISL29028
Electrical Specifications
V DD = 3.0V, T A = +25°C, R EXT = 499k Ω 1% tolerance. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN TYP MAX UNIT
I IRDR_LEAK IRDR Leakage Current
PROX_EN = 0; V DD = 3.63V (Note 8)
0.001
1
μA
V IRDR
t PULSE
V REF
F I2C
V I2C
Acceptable Voltage Range on IRDR Pin
Net I IRDR On Time Per PROX Reading
Voltage of R EXT Pin
I 2 C Clock Rate Range
Supply Voltage Range for I 2 C Interface
Register bit PROX_DR = 0
0.5
1.7
100
0.51
4.3
400
3.63
V
μs
V
kHz
V
V IL
V IH
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
1.25
0.55
V
V
I SDA
I INT
PSRR IRDR
SDA Current Sinking Capability
INT Current Sinking Capability
( Δ I IRDR )/( Δ V IRDR )
V OL = 0.4V
V OL = 0.4V
PROX_DR = 0; V IRDR = 0.5V to 4.3V
3
3
5
5
4
mA
mA
mA/V
NOTES:
6. An LED is used in production test. The LED irradiance is calibrated to produce the same DATA count against a fluorescent light
source of the same lux level.
7. An 850nm infrared LED is used to test PROX/IR sensitivity in an internal test mode.
8. Ability to guarantee I IRDR leakage of ~1nA is limited by test hardware.
9. For ALS applications under light-distorting glass, please see the section titled ALS Range 1 Considerations.
I2C Electrical Specifications For SCL and SDA unless otherwise noted, V DD = 3V, T A = +25°C, R EXT = 499k Ω 1%
tolerance (Note 10).
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP MAX UNIT
V I2C
Supply Voltage Range for I 2 C Interface
1.7
3.63
V
f SCL
V IL
V IH
V hys
V OL
SCL Clock Frequency
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
Hysteresis of Schmitt Trigger Input
Low-level output voltage (open-drain) at
4mA sink current
1.25
0.05V DD
400
0.55
0.4
kHz
V
V
V
V
I i
t SP
t AA
C i
Input Leakage for each SDA, SCL pin
Pulse Width of Spikes that must be
Suppressed by the Input Filter
SCL Falling Edge to SDA Output Data Valid
Capacitance for each SDA and SCL pin
-10
10
50
900
10
μA
ns
ns
pF
t HD:STA
t LOW
t HIGH
t SU:STA
t HD:DAT
t SU:DAT
t R
Hold Time (Repeated) START Condition
LOW Period of the SCL clock
HIGH period of the SCL Clock
Set-up Time for a Repeated START
Condition
Data Hold Time
Data Set-up Time
Rise Time of both SDA and SCL Signals
After this period, the first clock pulse
is generated
Measured at the 30% of VDD
crossing
(Note 11)
600
1300
600
600
30
100
20 + 0.1xC b
ns
ns
ns
ns
ns
ns
ns
4
FN6780.2
November 4, 2011
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